+1 862 207 3288 MIPS Computer Architecture
1. (6 points) Hazards. Consider the following code segment
lw $t0, 0($s0)
add $t3, $t0, $t1
sub $t4, $t3, $t2
(a) Identify the data hazards, if any, in the code that need to be resolved.
(b) How many cycles will this code take to execute on the pipelined machine from Figure 4.65 (with full forwarding support)?
(c) Assume we are trying to run this on a 5-stage MIPS pipelined processor with no forwarding support. Add nop instructions to the code in order to eliminate the data hazards.
2. (5 points) Pipeline Diagram. Fill in the pipeline diagram below for the following code, assuming it is running on the pipelined machine from Figure 4.65. Make sure to denote stalls and use arrows to show forwarding.
lw $t0, 0($s0)
addi $t2, $t0, 12
add $t1, $t0, $t0
lw $t3, 0($t1)
add $t0, $t0, $t3
add $t2, $t1, $t3
3. (5 points) Steady State CPI. For the following loop assume the 5-stage MIPS pipelined machine. Also assume the branch in the loop is taken 100000 times and that the branch is always predicted taken (the instruction that comes after the branch will always be the first instruction in the loop). Fill in the pipeline diagram below for one steady-state iteration of the loop (i.e. after it has been executing for a while) and calculate the steady-state CPI for the loop. The standard equation for steady-state CPI is: CPI = (#instructions+#stalls+#flushed instructions) / (#instructions)
loop: lw r1, 0 (r2)
add r1, r1, r8
sw r1, 0 (r2)
addi r2, r2, 4
bne r2, r7 loop
4. (3 points) Optimizing Code. For the code from question 3. If you had control of the compiler so you could move/change instructions within this loop (no loop unrolling) – what could you do to improve the CPI while still ensuring the same work is done? Show your new code. What is your new steady-state CPI? (Lower CPI receives more points).
5. (6 points) Forwarding Unit Logic. Consider the following code being executed on a 5-stage MIPS pipelined processor.
addi $t3, $s1, 15
add $t0, $t4, $t2
add $t1, $t4, $t1
sub $t7, $t6, $t2
List the pairs of registers that the forwarding unit is comparing during the 6th cycle of execution. Hint: Determine which instruction’s values are in the ID/EX, EX/MEM, and MEM/WB pipeline registers at the beginning of the 6th cycle, and then check the conditions for forwarding.
